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Full list of publications at Google Scholar
Conference Publications
C93 [GLSVLSI'25] D. Vungarala, M. Amin, A. Roohi, A. Ghosh, R. Zand, S. Angizi, “From Prompt to Accelerator: A Perspective on LLM-Based Analog In-Memory Accelerator Design Automation,” ACM Great Lakes Symposium on VLSI (GLSVLSI), New Orleans, LA, USA, June 30 - July 2, 2025. (Accepted)
C92 [GLSVLSI'25] S. Tabrizchi, A. Shafiee Sarvestani, M. Amin, D. Najafi, S. Angizi, R. Zand, and A. Roohi, “Magnetic In/Near-Sensor Architectures: From Raw Sensing to Smart Processing,” ACM Great Lakes Symposium on VLSI(GLSVLSI), New Orleans, LA, USA, June 30 - July 2, 2025. (Accepted)
C91 [GLSVLSI'25] G. Aragonda, D. Najafi, D. Vungarala, S. Tabrizchi, A. Roohi, and S. Angizi, “Maximizing Sub-Array Resource Utilization in Digital Processing-in-Memory: A Versatile Hardware-Aware Approach,” ACM Great Lakes Symposium on VLSI (GLSVLSI), New Orleans, LA, USA, June 30 - July 2, 2025. (Accepted)
C90 [GLSVLSI'25] N. Solanki, S. Tabrizchi, A. Shafiee Sarvestani, S. Angizi, and A. Roohi, “SenGuard: A Novel Processing In-Sensor Method for Privacy-Enhanced Smart Imaging,” ACM Great Lakes Symposium on VLSI (GLSVLSI), New Orleans, LA, USA, June 30 - July 2, 2025. (Accepted)
C89 [GLSVLSI'25] A. Almalky, R. Zhou, S. Angizi, and A. Siraj Rakin, “How Vulnerable are Large Language Models (LLMs) against Adversarial Bit-Flip Attacks?,” ACM Great Lakes Symposium on VLSI (GLSVLSI), New Orleans, LA, USA, June 30 - July 2, 2025. (Accepted)
C88 [GLSVLSI'25] M. Mohammadi, M. Morsali, S. Tabrizchi, B. Reidy, A. Roohi, S. Angizi, and R. Zand, “PixelPrune: Optimizing AIoT Vision Systems via In-Sensor Segmentation and Adaptive Data Transfer,” ACM Great Lakes Symposium on VLSI (GLSVLSI), New Orleans, LA, USA, June 30 - July 2, 2025. (Accepted)
C87 [GLSVLSI'25] M. Morsali, D. Najafi, A. Shafiee, S. Tabrizchi, P. Mercati, M. Imani, A. Roohi, N. Khoshavi, M. Nikdast, and S. Angizi, “Event-Driven Spatiotemporal Processing-In-Sensor with Phase Change Memory-based Optical Acceleration,” ACM Great Lakes Symposium on VLSI (GLSVLSI), New Orleans, LA, USA, June 30 - July 2, 2025. (Accepted)
C86 [ICCAD'25] A. Almalky, S. Ahmed, R. Zhou, M. Al Nahian, A. Al Arafat, S. Angizi, and A. Siraj Rakin, “LLWRA: Large Language Models Weight Replacement Attack,” IEEE/IFAC 9th International Conference on Control Automation and Diagnosis (ICCAD), Barcelona, Spain, July 1-3, 2025. (Accepted)
C85 [FCCM'25] D. Vungarala, M. H. Amin, P. Mercati, A. Roohi, R. Zand, and S. Angizi, “LLM-IMC: Automating Analog In-Memory Computing Architecture Generation with Large Language Models,” IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), Fayetteville, Arkansas, USA, May 4–7, 2025. (Accepted)
C84 [CVPR'25] S. Ahmed, A. Al Arafat, D. Najafi, A. Mahmood, M. Nayeem Rizve, M. Al Nahian, R. Zhou, S. Angizi, A. Siraj Rakin, “DeepCompress-ViT: Rethinking Model Compression to Enhance Efficiency of Vision Transformers at the Edge,” IEEE/CVF Computer Vision and Pattern Recognition Conference (CVPR), Nashville, TN, June 11-15, 2025. (Accepted)
C83 [GOMACTech'25] M. Morsali, D. Najafi, S. Angizi, M. Nikdast, “Boosting Near-Sensor Visual Processing with Silicon-Photonics-Enabled Edge Intelligence,” GOMACTech, Pasadena, CA, USA, March 17-20, 2025.
C82 [DAC'25] S. Tabrizchi, S. Sohrabi, M. Mohammadi, R. Zand, S. Angizi, and A. Roohi, “ResISC: Residue Number System-Based Integrated Sensing and Computing for Efficient Edge AI,” IEEE/ACM Design Automation Conference (DAC), San Francisco, CA, June 22-25, 2025. (Accepted)
C81 [ISCAS'25] D. Vungarala, M. Nazzal, M. Morsali, C. Zhang, A. Ghosh, A. Khreishah, and S. Angizi, “SA-DS: A Dataset for Large Language Model-Driven AI Accelerator Design Generation,” IEEE International Symposium on Circuits & Systems (ISCAS), London, UK, May 25-28, 2025. (Accepted)
C80 [DATE'25] R. Zhou, J. T. Liu, S. Ahmed, S. Angizi, and A. Siraj Rakin, “Compromising the Intelligence of Modern DNNs: On the Effectiveness of Targeted Row Press,” Design, Automation and Test in Europe (DATE), Lyon, France, 31 March - 2 April, 2025. (Accepted)
C79 [DATE'25] S. Jeong, H. Errahmouni Barkam, S. Yun, Y. Kim, S. Angizi, and M. Imani, “Exploiting Boosting in Hyperdimensional Computing for Enhanced Reliability in Healthcare,” Design, Automation and Test in Europe (DATE), Lyon, France, 31 March - 2 April, 2025. (Accepted)
C78 [ICRC'24] D. Vungarala, S. Alam, A. Ghosh, and S. Angizi, “SPICEPilot: Navigating SPICE Code Generation and Simulation with AI Guidance,” The 9th IEEE International Conference on Rebooting Computing (ICRC), San Diego, CA, USA, 16-17 December 2024. (Accepted)
C77 [ICCD'24] N. Taheri, S. Tabrizchi, S. Angizi, and A. Roohi, “ChaoSen: Security Enhancement of Image Sensor through in-Sensor Chaotic Computing,” IEEE International Conference on Computer Design (ICCD), Milan, Italy, November 18-20, 2024.
C76 [MWSCAS'24] R. Gaire, S. Tabrizchi, D. Najafi, S. Angizi, and A. Roohi, “DECO: Dynamic Energy-Aware Compression and Optimization for In-Memory Neural Networks,” IEEE 66th International Midwest Symposium on Circuits and Systems (MWSCAS), Springfield, Massachusetts, USA, August 11-14, 2024.
C75 [ISVLSI'24] M. Morsali, S. Tabrizchi, R. Teja Velpula, M. Bala Sankar Muthu, H. Pham Trung Nguyen, M. Imani, A. Roohi, and S. Angizi, “Energy-Efficient Near-Sensor Event Detector based on Multilevel Ga2O3 RRAM,” IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Knoxville, Tennessee, USA July 1-3, 2024.
C74 [ISVLSI'24] N. Taheri, S. Tabrizchi, D. Najafi, S. Angizi, and A. Roohi, “ResSen: Imager Privacy Enhancement through Residue Arithmetic Processing in Sensors,” IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Knoxville, Tennessee, USA July 1-3, 2024.
C73 [GLSVLSI'24] D. Najafi, S. Tabrizchi, R. Zhou, M. Amel Solouki, A. Marshal, A. Roohi, and S. Angizi, “Hybrid Magneto-electric FET-CMOS Integrated Memory Design for Instant-on Computing,” 34th edition of Great Lakes Symposium on VLSI (GLSVLSI), Tampa Bay Area, FL, USA, June 12-14, 2024.
C72 [GLSVLSI'24] S. Tabrizchi, N. Taheri, S. Angizi, and A. Roohi, “RACSen: Residue Arithmetic and Chaotic Processing in Sensors to Enhance CMOS Imager Security,” 34th edition of Great Lakes Symposium on VLSI (GLSVLSI), Tampa Bay Area, FL, USA, June 12-14, 2024.
C71 [CVPR'24] S. Ahmed, R. Zhou, S. Angizi, and A. Rakin, “Deep-TROJ: An Inference Stage Trojan Insertion Algorithm through Efficient Weight Replacement Attack,” IEEE/CVF Computer Vision and Pattern Recognition Conference (CVPR), Seattle, WA, USA, June 17-21, 2024.
C70 [DAC'24] M. Morsali, B. Reidy, D. Najafi, S. Tabrizchi, M. Imani, M. Nikdast, A. Roohi, R. Zand, S. Angizi, “Lightator: An Optical Near-Sensor Accelerator with Compressive Acquisition Enabling Versatile Image Processing,” IEEE/ACM Design Automation Conference (DAC), San Francisco, CA, USA, June 23-27, 2024.
C69 [DAC'24] R. Zhou, S. Ahmed, A. Rakin, S. Angizi, “DNN-Defender: A Victim-Focused In-DRAM Defense Mechanism for Taming Adversarial Weight Attack on DNNs,” IEEE/ACM Design Automation Conference (DAC), San Francisco, CA, USA, June 23-27, 2024.
C68 [DAC'24] B. Reidy, S. Tabrizchi, M. Mohammadi, S. Angizi, A. Roohi, and R. Zand, “HiRISE: High-Resolution Image Scaling for Edge ML via In-Sensor Compression and Selective ROI,” IEEE/ACM Design Automation Conference (DAC), San Francisco, CA, USA, June 23-27, 2024.
C67 [DATE'24] M. Morsali, S. Tabrizchi, D. Najafi, M. Imani, M. Nikdast, A. Roohi, and S. Angizi, “OISA: Architecting an Optical In-Sensor Accelerator for Efficient Visual Computing,” Design, Automation and Test in Europe (DATE), Valencia, Spain, March 25-27, 2024.
C66 [DATE'24] R. Zhou, S. Ahmed, A. Roohi, A. Rakin, S. Angizi, “DRAM-Locker: A General-Purpose DRAM Protection Mechanism against Adversarial DNN Weight Attacks,” Design, Automation and Test in Europe (DATE), Valencia, Spain, March 25-27, 2024.
C65 [DATE'24] S. Tabrizchi, S. Angizi, and A. Roohi, “DIAC: Design Exploration of Intermittent-Aware Computing Realizing Batteryless Systems ,” Design, Automation and Test in Europe (DATE), Valencia, Spain, March 25-27, 2024.
C64 [ICRC'23] M. Morsali, S. Tabrizchi, M. Liehr, N. Cady, M. Imani, A. Roohi, and S. Angizi, “Deep Mapper: A Multi-Channel Single-Cycle Near-Sensor DNN Accelerator,” The 8th IEEE International Conference on Rebooting Computing (ICRC), San Diego, CA, USA, December 5-6, 2023.
C63 [MWSCAS'23] D. Vungarala, M. Morsali, S. Tabrizchi, A. Roohi, and S. Angizi, “Comparative Study of Low Bit-width DNN Accelerators: Opportunities and Challenges,” IEEE 66th International Midwest Symposium on Circuits and Systems (MWSCAS), Phoenix, Arizona, USA, Aug 6-9, 2023.
C62 [ISLPED'23] S. Tabrizchi, S. Angizi, and A. Roohi, “Ocellus: Highly Parallel Convolution-in-Pixel Scheme Realizing Power-Delay-Efficient Edge Intelligence,” IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), Vienna, Austria, August 7-8, 2023.
C61 [GLSVLSI'23] M. Morsali, M. Nazzal, A. Khreishah, and S. Angizi, “IMA-GNN: In-Memory Acceleration of Centralized and Decentralized Graph Neural Networks at the Edge,” 33rd edition of Great Lakes Symposium on VLSI (GLSVLSI), Knoxville, TN, USA, June 5-7, 2023.
(Best Paper Award)
C60 [GLSVLSI'23] S. Tabrizchi, R. Gaire, S. Angizi, and A. Roohi, “SenTer: A Reconfigurable Processing-in-Sensor Architecture Enabling Efficient Ternary MLP,” 33rd edition of Great Lakes Symposium on VLSI (GLSVLSI), Knoxville, TN, USA, June 5-7, 2023.
C59 [GLSVLSI'23] N. Kochar, L. Ekiert, D. Najafi, D. Fan, and S. Angizi, “Accelerating Low Bit-width Neural Networks at the Edge, PIM or FPGA: A Comparative Study,” 33rd edition of Great Lakes Symposium on VLSI (GLSVLSI), Knoxville, TN, USA, June 5-7, 2023.
C58 [ISQED'23] M. Morsali, R. Zhou, S. Tabrizchi, A. Roohi, and S. Angizi, “XOR-CiM: An Efficient Computing-in-SOT-MRAM Design for Binary Neural Network Acceleration,” International Symposium on Quality Electronic Design (ISQED), San Francisco, California, USA, April 5-7, 2023.
C57 [ISCAS'23] S. Tabrizchi, M. Morsali, S. Angizi, and A. Roohi, “NeSe: Near-Sensor Event-Driven Scheme for Low Power Energy
Harvesting Sensors,” IEEE International Symposium on Circuits & Systems (ISCAS), Monterey, California, USA, May 21-25, 2023.
C56 [DATE'23] R. Zhou, S. Tabrizchi, M. Morsali, A. Roohi, and S. Angizi, “P-PIM: A Parallel Processing-in-DRAM Framework Enabling RowHammer Protection,” Design, Automation and Test in Europe (DATE), Antwerp, Belgium, April 17-19, 2023.
C55 [IGSC'22] E. Lattanzio, R. Zhou, A. Roohi, A. Khreishah, D. Misra, and S. Angizi, “Toward a Behavioral-Level End-To-End Framework for Silicon Photonics Accelerators,” IEEE International Green and Sustainable Computing Conference (IGSC), Virtual, October 24 - 25, 2022.
C54 [ICMLA'22] A. Nezhadi, S. Angizi, and A. Roohi, “semiMul: Floating-Point Free Implementations for Efficient and Accurate Neural Network Training,” IEEE International Conference on Machine Learning and Applications (ICMLA), Nassau, The Bahamas, December 12 - 15, 2022.
C53 [ICCD'22] S. Tabrizchi, S. Angizi, and A. Roohi, “TizBin: A Low-Power Image Sensor with Event and Object Detection Using Efficient Processing-in-Pixel Schemes,” IEEE International Conference on Computer Design (ICCD), Lake Tahoe, USA, October 23 - 26, 2022.
C52 [ICCAD'22] R. Zhou, A. Roohi, D. Misra, and S. Angizi, “ReD-LUT: Reconfigurable In-DRAM LUTs Enabling Massive Parallel Computation,” International Conference on Computer Aided Design (ICCAD), San Diego, California, USA, 30 October - 3 November, 2022.
C51 [ESWEEK'22] M. Abedin, A. Roohi, N. Cady, and S. Angizi, “A Processing-in-Pixel Accelerator based on Multi-level HfOx ReRAM,” Embedded Systems Week- International Conference on Compilers, Architectures, and Synthesis for Embedded Systems (ESWEEK-CASES), Hybrid-Shanghai, October 07-14, 2022.
C50 [ESSCIRC'22] S. Angizi, A. Sridharan, S. Kiran Cherupally, F. Zhang, J. Seo, and D. Fan, “A 1.23-GHz 16-Kb Programmable and Generic Processing-in-SRAM Accelerator in 65nm,” European Solid-State Circuits Conference (ESSCIRC), Milan, Italy, September 19-22, 2022.
C49 [ISLPED'22] R. Zhou, A. Roohi, D. Misra, and S. Angizi, “FlexiDRAM: A Flexible in-DRAM Framework to Enable Parallel General-Purpose Computation,” IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), Boston, MA, USA, August 1-3, 2022.
C48 [MWSCAS'22] S. Tabrizchi, S. Angizi, and A. Roohi, “Design and Evaluation of a Robust Power-Efficient Ternary SRAM Cell,” 65th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Virtual, August 7-10, 2022.
C47 [DCAS'22] A. Nezhadi, S. Angizi, and A. Roohi, “EaseMiss: HW/SW Co-Optimization for Efficient Large Matrix-Matrix Multiply Operations,” IEEE Dallas Circuits and Systems (DCAS), Virtual, June 17-19, 2022.
C46 [HOST'22] A. Roohi and S. Angizi, “Efficient Targeted Bit-Flip Attack Against the Local Binary Pattern Network,” IEEE International Symposium on Hardware Oriented Security and Trust (HOST), Washington DC, USA, June 27-30, 2022.
C45 [ISCAS'22] S. Tabrizchi, S. Angizi, and A. Roohi, “SCiMA: a Generic Single-Cycle Compute-in-Memory Acceleration Scheme for Matrix Computations,” IEEE International Symposium on Circuits & Systems (ISCAS), Virtual, 28 May-01 June, 2022.
C44 [ISQED'22] S. Angizi, and A. Roohi, “Integrated Sensing and Computing using Energy-Efficient Magnetic Synapses,” International Symposium on Quality Electronic Design (ISQED), Virtual, 6-8 April, 2022.
C43 [ISQED'22] A. Roohi, S. Angizi, P. NavaeiLavasani, M. Taheri, “ReFACE: Efficient Design Methodology for Acceleration of Digital Filter Implementations,” International Symposium on Quality Electronic Design (ISQED), Virtual, 6-8 April, 2022.
C42 [ICCAD'21] A. Roohi, M. Taheri, S. Angizi, and D. Fan, “RNSiM: Efficient Deep Neural Network Accelerator Using Residue Number Systems,” International Conference on Computer Aided Design (ICCAD), Nov. 1-4, 2021
C41 [GLSVLSI'21] S. Angizi, A. Roohi, M. Taheri, and D. Fan, “Processing-in-Memory Acceleration of MAC based Applications Using Residue Number System: A Comparative Study,” 31st edition of Great Lakes Symposium on VLSI (GLSVLSI), Virtual, June 22-25, 2021.
C40 [DAC'21] F. Zhang, S. Angizi and D. Fan, “Max-PIM: Fast and Efficient Max/Min Searching in DRAM,” IEEE/ACM Design Automation Conference (DAC), San Francisco, CA, July 11-15, 2021.
C39 [DAC'21] F. Zhang, S. Angizi, N. Ahmed Fahmi, W. Zhang, and D. Fan, “PIM-Quantifier: A Processing-in-Memory Platform for Genome Quantification,” IEEE/ACM Design Automation Conference (DAC), San Francisco, CA, July 11-15, 2021.
C38 [SOCC’20] L. Yang, Z. He, S. Angizi and D. Fan, “Processing-In-Memory Accelerator for Dynamic Neural Network with Run-Time Tuning of Accuracy, Power and Latency,”33rd IEEE International System-on-Chip Conference (SOCC), September 8-11, 2020 (invited).
C37 [GLSVLSI’20] S. Angizi, W. Zhang and D. Fan, “Exploring DNA Alignment-in-Memory Leveraging Emerging SOT-MRAM,”30th edition of the ACM Great Lakes Symposium on VLSI (GLSVLSI), Beijing, China, September 8-11, 2020 (Virtual).
C36 [GLSVLSI’20] D. Reis, D. Gao, S. Angizi, X. Yin, D. Fan, M. Niemier, C. Zhuo and X.S. Hu„ “Modeling and Benchmarking Computing-in-Memory for Design Space Exploration,”30th edition of the ACM Great Lakes Symposium on VLSI(GLSVLSI), Beijing, China, September 8-11, 2020 (Virtual).
C35 [DAC’20] S. Angizi, N. Ahmed Fahmi, W. Zhang, and D. Fan, “PIM-Assembler: A Processing-in-Memory Platform for Genome Assembly,” IEEE/ACM Design Automation Conference (DAC), San Francisco, CA, July 19-23, 2020.
C34 [DATE’20] S. Angizi, J. Sun, W. Zhang, and D. Fan, “PIM-Aligner: A Processing-in-MRAM Platform for Biological Sequence Alignment,” Design, Automation and Test in Europe (DATE), 09-13 March 2020, ALPEXPO, Grenoble, France.
C33 [ASPDAC’20] L. Yang, S. Angizi, and D. Fan, “A Flexible Processing-in-Memory Accelerator for Dynamic Channel-Adaptive Deep Neural Networks,” Asia and South Pacific Design Automation Conference (ASP-DAC) Jan. 13-16, 2020, Beijing, China.
C32 [ISVLSI’19] S. Angizi, Z. He, D. Reis, X. S. Hu, W. Tsai, S. J. Lin, and D. Fan, “Accelerating Deep Neural Networks in Processing-in-Memory Platforms: Analog or Digital Approach?,” IEEE Computer Society Annual Symposium on VLSI (ISVLSI) , June 15-17, 2019, Las Vegas, Miami, Florida, USA.
C31 [NANOARCH’19] S. Angizi and D. Fan, “Deep Neural Network Acceleration in Non-Volatile Memory: A Digital Approach?,” IEEE/ACM International Symposium on Nanoscale Architectures, 17-19 July 2019, Qingdao, CHINA.
C30 [ICCAD’19] S. Angizi, and D. Fan, “ReDRAM: A Reconfigurable Processing-in-DRAM Platform for Accelerating Bulk Bit-Wise Operations,” IEEE/ACM International Conference on Computer Aided Design (ICCAD), 4-7 November 2019, Westminster, CO, USA.
C29 [DAC’19] S. Angizi, J. Sun, W. Zhang and D. Fan, “AlignS: A Processing-In-Memory Accelerator for DNA Short Read Alignment Leveraging SOT-MRAM,” IEEE/ACM Design Automation Conference (DAC), June 2-6, 2019, Las Vegas, NV, USA.
C28 [GLSVLSI’19] S. Angizi and D. Fan, “GraphiDe: A Graph Processing Accelerator leveraging In-DRAM-Computing,” ACM Great Lakes Symposium on VLSI (GLSVLSI) , May 9-11, 2019, Washington, D.C., USA. (Best Paper Award)
C27 [DATE’19] S. Angizi, J. Sun, W. Zhang and D. Fan, “GraphS: A Graph Processing Accelerator Leveraging SOT-MRAM,” Design, Automation and Test in Europe (DATE), March 25-29, 2019, Florence, Italy.
C26 [ASPDAC’19] S. Angizi, Z. He and D. Fan, “ParaPIM: A Parallel Processing-in-Memory Accelerator for Binary-Weight Deep Neural Networks,” Asia and South Pacific Design Automation Conference (ASP-DAC), Jan. 21-24, 2019, Tokyo, Japan.
C25 [ISQED’19] A. Roohi, S. Angizi, D. Fan and R. F. DeMara, “Processing-In-Memory Acceleration of Convolutional Neural Networks for Energy-Efficiency, and Power-Intermittency Resilience,” International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, USA, 6-7 March, 2019.
C24 [ICCD’18] A. Rakin, S. Angizi, Z. He and D. Fan, “PIM-TGAN: A Processing-in-Memory Accelerator for Ternary Generative Adversarial Networks,” IEEE International Conference on Computer Design (ICCD), Oct. 7-10, 2018, Orlando, FL, USA.
C23 [ICCAD’18] S. Angizi, Z. He and D. Fan, “DIMA: A Depthwise CNN In-Memory Accelerator,” IEEE/ACM International Conference on Computer Aided Design (ICCAD), Nov. 5-8, 2018, San Diego, CA, USA.
C22 [ISVLSI’18] Z. He, S. Angizi, A. Rakin and D. Fan, “BD-NET: A Multiplication-less DNN with Binarized Depthwise Separable Convolution,” IEEE Computer Society Annual Symposium on VLSI, July 9-11, 2018, Hong Kong, CHINA. (Best Paper Award)
C21 [ISVLSI’18] Z. He, S. Angizi and D. Fan, “Accelerating Low Bit-Width Deep Convolution Neural Network in MRAM,” IEEE Computer Society Annual Symposium on VLSI , July 9-11, 2018, Hong Kong, CHINA.
C20 [GLSVLSI’18] S. Angizi, Z. He, Y. Bai, R. F. DeMara, J. Han, M. Lin and D. Fan, “Leveraging Spintronic Devices for Efficient Approximate Logic and Stochastic Neural Network,” ACM Great Lakes Symposium on VLSI (GLSVLSI), May 23-25, 2018 Chicago, IL, USA.
C19 [DAC’18] S. Angizi , Z. He, A. Rakin and D. Fan, “CMP-PIM: An Energy-Efficient Comparator-based Processing-In-Memory Neural Network Accelerator,” IEEE/ACM Design Automation Conference (DAC), June 24-28, 2018, San Francisco, CA, USA.
C18 [DAC’18] S. Angizi, Z. He and D. Fan, “PIMA-Logic: A Novel Processing-in-Memory Architecture for Highly Flexible and Energy-Efficient Logic Computation,” IEEE/ACM Design Automation Conference (DAC), June 24-28, 2018, San Francisco, CA, USA.
C17 [ASPDAC’18] S. Angizi, Z. He, F. Parveen and D. Fan, “IMCE: Energy-Efficient Bit-Wise In-Memory Convolution Engine for Deep Neural Network,” Asia and South Pacific Design Automation Conference (ASP-DAC), Jan. 22-25, 2018, Jeju Island, Korea.
C16 [ASPDAC’18] F. Parveen, Z. He, S. Angizi and D. Fan, “HieIM: Highly Flexible In-Memory Computing using STT MRAM,” Asia and South Pacific Design Automation Conference (ASP-DAC), Jan. 22-25, 2018, Jeju Island, Korea.
C15 [NCAMA’17] S. Angizi and D. Fan, “IMC: Energy-Efficient In-Memory Convolver for Accelerating Binarized Deep Neural Network,” Neuromorphic Computing Symposium: Architectures, Models, and Applications, July 17-19, 2017, Knoxville, Tennessee.
C14 [ICCD’17] D. Fan and S. Angizi, “Energy Efficient In-Memory Binary Deep Neural Network Accelerator with Dual-Mode SOT-MRAM,” IEEE International Conference on Computer Design (ICCD), Nov. 5-8, 2017, Boston, MA.
C13 [ICCD’17] Z. He, S. Angizi, and D. Fan, “Exploring STT-MRAM based In-Memory Computing Paradigm with Application of Image Edge Extraction,” IEEE International Conference on Computer Design (ICCD), Nov. 5-8, 2017, Boston, MA.
C12 [ISLPED’17] F. Parveen, S. Angizi, Z. He and D. Fan, “Low Power In-Memory Computing based on Dual-Mode SOT- MRAM,” IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), July 24-26, 2017, Taipei, Taiwan.
C11 [NANOARCH’17] Z. He, S. Angizi, F. Parveen and D. Fan, “High Performance and Energy-Efficient In-Memory Computing Architecture based on SOT-MRAM,” IEEE/ACM International Symposium on Nanoscale Architectures, July 25- 26, 2017, Newport, USA.
C10 [ISVLSI’17] D. Fan, S. Angizi and Z. He, “In-Memory Computing with Spintronic Devices,” IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 3-5, 2017, Bochum, Germany (invited).
C9 [ISVLSI’17] S. Angizi, Z. He, F. Parveen and D. Fan, “RIMPA: A New Reconfigurable Dual-Mode In-Memory Processing Architecture with Spin Hall Effect-Driven Domain Wall Motion Device,” IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 3-5, 2017, Bochum, Germany.
C8 [ISVLSI’17] F. Parveen, Z. He, S. Angizi and D. Fan, “Hybrid Polymorphic Logic Gate with 5-Terminal Magnetic Domain Wall Motion Device,” IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 3-5, 2017, Bochum, Germany. (Best Paper Award)
C7 [MWSCAS’17] D. Fan, Z. He and S. Angizi, “Leveraging Spintronic Devices for Ultra-Low Power In-Memory Computing: Logic and Neural Network,” 60th IEEE International Midwest Symposium on Circuits and System (MWSCAS), Aug. 6-9, 2017, Boston, MA, USA (invited)
C6 [ISCAS’17] F. Parveen, S. Angizi, Z. He and D. Fan, “Hybrid Polymorphic Logic Gate Using 6 Terminal Magnetic Domain Wall Motion Device,” IEEE International Symposium on Circuits & Systems (ISCAS), Baltimore, MD, USA, May 28-31, 2017.
C5 [GLSVLSI’17] S. Angizi, Z. He, and D. Fan, “Energy Efficient In-Memory Computing Platform Based on 4-Terminal Spin Hall Effect-Driven Domain Wall Motion Devices”, 27th GLSVLSI, Banff, Alberta, Canada, May 10-12, 2017.
C4 [GLSVLSI’17] Z. He, S. Angizi, F. Parveen, and D. Fan, “Leveraging Dual-Mode Magnetic Crossbar for Ultra-low Energy In- Memory Data Encryption”, 27th GLSVLSI, Banff, Alberta, Canada, May 10-12, 2017.
C3 [ISQED’17] S. Angizi, Z. He, R. DeMara and D. Fan, “Composite Spintronic Accuracy-Configurable Adder for Low Power Digital Signal Processing,” 18th International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, USA, 13-15 March, 2017.
C2 [CADS’15] A. M. Chabi, A. Roohi, R. F. DeMara, S. Angizi, K. Navi, and H. Khademolhosseini, "Cost-efficient QCA reversible combinational circuits based on a new reversible gate," in Computer Architecture and Digital Systems (CADS), 2015 18th IEEE CSI International Symposium on, 2015, pp. 1-6.
C1 [INIS’15] M. R. Jahangir, S. Sheikhfaal, S. Angizi, K. Navi, and F. Ahmad, Designing Nanoelectronic-compatible 8-bit Square Root Circuit by Quantum-dot Cellular Automata, In Proceeding of The IEEE International Symposium on Nanoelectronic and Information Systems, Indore, India, December 21st-23rd, 2015.
Peer-Reviewed Journal Publications
J59 [TCASAI'25] D. Najafi, H. Errahmouni Barkam, M. Morsali, S. Jeong, T. Das, A. Roohi, M. Nikdast, M. Imani, and S. Angizi ,“Neuro-Photonix: Enabling Near-Sensor Neuro-Symbolic AI Computing on Silicon Photonics Substrate”, IEEE Transactions on Circuits and Systems for Artificial Intelligence (TCASAI), IEEE, 2025.
J58 [CAL'24] S. Tabrizchi, M. Morsali, D. Z. Pan, S. Angizi, and A. Roohi, “PINSim: A Processing In- and Near-Sensor Simulator to Model Intelligent Vision Sensors”, IEEE Computer Architecture Letters (CAL), IEEE, Vol. 24, No. 1, pp. 17-20, 2024.
J57 [ACCESS'24] M. Amel Solouki, S. Angizi, and M. Violante, “Dependability in Embedded Systems: A Survey of Fault Tolerance Methods and Software-Based Mitigation Techniques”, IEEE Access, IEEE, Vol. 12, pp. 180939-180967, 2024.
J56 [TCAD'24] R. Zhou, J. Liu, S. Ahmed, N. Kochar, A. Siraj Rakin, and S. Angizi, “Assessing the Potential of Escalating RowHammer Attack Distance to Bypass Counter-based Defenses”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), IEEE, 2024.
J55 [TETC'24] S. Tabrizchi, R. Gaire, M. Morsali, M. Liehr, N. Cady, S. Angizi, and A. Roohi, “APRIS: Approximate Processing ReRAM In-Sensor Architecture Enabling Artificial-Intelligence-Powered Edge”, IEEE Transactions on Emerging Topics in Computing (TETC), IEEE, 2024.
J54 [CASM'24] S. Angizi, and D. Misra, “CASS Chapter Highlights”, IEEE Circuits and Systems Magazine (CASM), IEEE, Vol. 24, No. 4, pp. 91-94, 2024
J53 [ESL'24] R. Zhou, J. Liu, N. Kochar, S. Ahmed, A. Siraj Rakin, and S. Angizi , “A Novel Insight into the Vulnerability of DDR4 DRAM Cells Across Multiple Hammering Settings”, IEEE Embedded Systems Letters (ESL), IEEE, Vol. 16, No. 4, pp. 337 - 340, 2024.
J52 [ESL'24] S. Tabrizchi, B. C. Reidy, D. Najafi, S. Angizi , R. Zand, and A. Roohi, “ViTSen: Bridging Vision Transformers and Edge Computing with Advanced In/Near-Sensor Processing”, IEEE Embedded Systems Letters (ESL), IEEE, Vol.16, No. 4, pp. 341 - 344, 2024.
J51 [TED'24] D. Najafi, M. Morsali, R. Zhou, A. Roohi, A. Marshall, D. Misra, and S. Angizi, “Enabling Normally-off In-Situ Computing with a Magneto-Electric FET-based SRAM Design”, IEEE Transactions on Electron Devices (TED), IEEE, Vol. 71, No. 4, pp. 2742 - 2748, 2024.
J50 [AISY'24] S. Yun, H. Chen, R. Masukawa, H. Errahmouni Barkam, A. Ding, W. Huang, A. Rezvani, S. Angizi, and M. Imani “HyperSense: Hyperdimensional Intelligent Sensing for Energy-Efficient Sparse Data Processing”, Advanced Intelligent Systems, WILEY, 2024.
J49 [TVT'24] M. Nazzal, A. Khreishah, J. Lee, S. Angizi , A. Al-Fuqaha, and M. Guizani, “Semi-decentralized Inference in Heterogeneous Graph Neural Networks for Traffic Demand Forecasting: An Edge-Computing Approach”, IEEE Transactions on Vehicular Technology (TVT), IEEE, Vol. 73, No. 12, pp. 19400 - 19416, 2024.
J48 [JLPEA'24] S. Angizi, N. Ahmed Fahmi, D. Najafi, W. Zhang, and D. Fan , “PANDA: Processing in Magnetic Random-Access Memory- Accelerated de Bruijn Graph-Based DNA Assembly”, Journal of Low Power Electronics and Applications (JLPEA), MDPI, Vol. 14, No. 1, 2024
J47 [TCAD'23] A. Roohi, S. Tabrizchi, M. Morsali, D. Pan, and S. Angizi, “PiPSim: A Behavior-Level Modeling Tool for CNN Processing-in-Pixel Accelerators”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), IEEE, Vol. 43, No. 1, pp. 141 - 150, 2024.
J46 [TED'23] M. Morsali, S. Tabrizchi, A. Marshall, A. Roohi, D. Misra, and S. Angizi, “Design and Evaluation of a Near-Sensor Magneto-Electric
FET-based Event Detector”, IEEE Transactions on Electron Devices (TED), IEEE, Vol. 70, No. 9, pp. 4822-4828, 2023.
J45 [TETC'23] S. Angizi, S. Tabrizchi, D. Pan and A. Roohi, “PISA: A Non-Volatile Processing-In-Sensor Accelerator for Imaging Systems”, IEEE Transactions on Emerging Topics in Computing (TETC), IEEE, Vol. 11, No. 4, pp. 962 - 972, 2023.
J44 [TETC'23] S. Angizi, M. Morsali, S. Tabrizchi, and A. Roohi, “A Near-Sensor Processing Accelerator for Approximate Local Binary Pattern Networks”, IEEE Transactions on Emerging Topics in Computing (TETC), IEEE, 2023.
J43 [JETCAS'23] S. Tabrizchi, A. Nezhadi, S. Angizi, and A. Roohi, “AppCiP: Energy-Efficient Approximate Convolution-in-Pixel Scheme for Neural Network Acceleration”, IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), IEEE, Vol. 13, No. 1, pp. 225-236, 2023.
J42 [JETCAS'23] F. Zhang, S. Angizi, J. Sun, W. Zhang, and D. Fan, “Aligner-D: Leveraging in-DRAM Computing to Accelerate DNA Short Read Alignment”, IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), IEEE, Vol. 13, No. 1, pp. 332-343, 2023.
J41 [CAL'22] R. Zhou, S. Tabrizchi, A. Roohi, and S. Angizi, “LT-PIM: An LUT-based Processing-in-DRAM Architecture with RowHammer Self-Tracking”, IEEE Computer Architecture Letters (CAL), IEEE, Vol. 21, No. 2, pp. 141 - 144, 2022.
J40 [JLPEA'22] S. Tabrizchi, S. Angizi, and A. Roohi, “Ocelli: Efficient Processing-in-Pixel Array Enabling Edge Inference of Ternary Neural Networks”, Journal of Low Power Electronics and Applications (JLPEA), MDPI, Vol. 12, No. 4, 2022.
J39 [JXCDC'22] M. Abedin, A. Roohi, M. Liehr, N. Cady, and S. Angizi, “MR-PIPA: An Integrated Multi-level RRAM (HfOx) based Processing-In-Pixel Accelerator”, IEEE Journal on Exploratory Solid-State Computational Devices and Circuits (JXCDC), IEEE, Vol. 8, No. 2, pp. 59 - 67
J38 [TETC'22] S. Sheikhfaal, S. Angizi, and R. F. DeMara, “Energy-Efficient Recurrent Neural Network with MRAM-based Probabilistic Activation Functions”, IEEE Transactions on Emerging Topics in Computing (TETC), IEEE, 2022.
J37 [Micromachines'22] M. H. Alali, A. Roohi, S. Angizi, and J. S. Deogun, “Enabling Intelligent IoTs for Histopathology Image Analysis Using Convolutional Neural Networks,” Micromachines, MDPI, Vol. 13, No. 8, 2022.
J36 [TODAES'21] S. Angizi, N. Khoshavi, A. Marshall, P. Dowben and D. Fan, “MeF-RAM: A New Non-Volatile Cache Memory Based on Magneto-Electric FET,” ACM Transactions on Design Automation of Electronic Systems, (TODAES), ACM, Vol. 27, No. 2, pp. 1–18, 2021.
J35 [TCASI'20] H. Jiang, S. Angizi, D. Fan, J. Han and L. Liu “Non-Volatile Approximate Arithmetic Circuits using Scalable Hybrid Spin-CMOS Majority Gates,” IEEE Transactions on Circuits and Systems I: Regular Papers (TCASI), IEEE, Vol. 68, No. 3, pp. 1217-1230, 2021.
J34 [TC’20] A. Roohi, S. Sheikhfaal, S. Angizi, D. Fan and R. F. DeMara, “ApGAN: Approximate GAN for Robust Low Energy Learning from Imprecise Components,” IEEE Transactions on Computers, IEEE, Vol. 69, No. 3, March 2020.
J33 [TMAG’20] S. Angizi, Z. He, A. Chen and D. Fan, “Hybrid Spin-CMOS Polymorphic Logic Gate with Application in In-Memory Computing,” IEEE Transactions on Magnetics, IEEE, Vol. 56, No. 2, 2020.
J32 [JETC’19] L.Yang, Z. He, S. Angizi, A. Rakin and D. Fan, “Sparse BD-Net: A Multiplication-Less DNN with Sparse Binarized Depth-wise Separable Convolution,” ACM Journal on Emerging Technologies in Computing Systems (JETC), Vol. 16, No. 2, 2019.
J31 [TCAD’19] S. Angizi, Z. He, A. Awad and D. Fan, “MRIMA: An MRAM-based In-Memory Accelerator,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE, 2019.
J30 [TNANO’18] S. Angizi, H. Jiang, R. F. Demara, J. Han and D. Fan, “Majority-Based Spin-CMOS Primitives for Approximate Computing,” IEEE Transactions on Nanotechnology, IEEE, Vol. 17, No. 4, pp. 795-806, 2018.
J29 [TMSCS’18] Z. He, Y. Zhang, S. Angizi, B. Gong and D. Fan, “Exploring A SOT-MRAM based In-Memory Computing for Data Processing,” IEEE Transactions on Multi-Scale Computing Systems, IEEE, Vol. 4, No. 4, pp. 676-685, 2018.
J28 [TMAG’18] F. Parveen, S. Angizi, Z. He and D. Fan, “IMCS2: Novel Device-to-Architecture Co-design for Low Power In-memory Computing Platform using Coterminous Spin-Switch,” IEEE Transactions on Magnetics, IEEE, Vol. 54, No. 7, 2018.
J27 [JETC’18] F. Parveen, S. Angizi and D. Fan, “ IMFlexCom: Energy Efficient In-memory Flexible Computing using Dual-mode SOT-MRAM,” ACM Journal on Emerging Technologies in Computing Systems, ACM, Vol. 14, No. 3, 2018.
J26 [JSS’18] S. Azimi, S. Angizi and M. H. Moaiyeri, “Efficient and Robust SRAM Cell Design Based on Quantum-Dot Cellular Automata,” ECS Journal of Solid State Science and Technology, The Electrochemical Society, Vol. 7, No.3, pp. Q38-Q45, 2018.
J25 [JNO’18] H. Khademolhosseini, S. Angizi and Y. Nemati, “A Fault-Tolerant Design for 3-Input Majority Gate in Quantum-Dot Cellular Automata,” Journal of Nanoelectronics and Optoelectronics, ASP, Vol. 13, No. 1, 2018.
J24 [TCAD’18] S. Angizi, Z. He, N. Bagherzadeh and D. Fan, “Design and Evaluation of a Spintronic In-Memory Processing Platform for Non-Volatile Data Encryption,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE, Vol. 37, No.9, pp. 1788-1801, 2018.
J23 [MICT’17] M. H. Moaiyeri, F. Sabetzadeh, and S. Angizi, “An efficient majority-based compressor for approximate computing in the nano era,” Microsystem Technologies, Springer, Vol. 24, No. 3, pp.1589–1601, 2017.
J22 [MAGL’17] Z. He, S. Angizi, and D. Fan, “Current Induced Dynamics of Multiple Skyrmions with Domain Wall Pair and Skyrmion-based Majority gate Design”, IEEE Magnetics Letters, IEEE, Vol. 8, March 30, 2017.
J21 [OPT’17] E. Taherkhani, M. H. Moaiyeri, and S. Angizi, “Design of an Ultra-Efficient Reversible Full Adder-Subtractor in Quantum-dot Cellular Automata,” Optik-International Journal for Light and Electron Optics, Elsevier, Vol. 142, August 2017, pp. 557-563, 2017.
J20 [MICPRO’17] M. B. Khosroshahy, M. H. Moaiyeri, S. Angizi, N. Bagherzadeh, and K. Navi, "Quantum-Dot Cellular Automata Circuits with Reduced External Fixed Inputs," Microprocessors and Microsystems, Elsevier, Vol. 50, May 2017, pp. 154-163, 2017.
J19 [JOLPE’17] Z. Rouhani, S. Angizi, M. Taheri, K. Navi, and N. Bagherzadeh, "Towards Approximate Computing with Quantum- Dot Cellular Automata," Journal of Low Power Electronics, ASP, Vol. 13, No. 1, pp. 29-35, 2017.
J18 [MICPRO’17] A. M. Chabi, A. Roohi, H. Khademolhosseini, S. Sheikhfaal, S. Angizi, K. Navi, and R. F. DeMara, “Towards ultra-efficient QCA reversible circuits,” Microprocessors and Microsystems, Vol. 49, pp. 127-138, 2017. Page 4 /7
J17 [TETC’16] A. Roohi, R. Zand, S. Angizi, and R. F. DeMara, “A Parity-Preserving Reversible QCA Gate with Self-Checking Cascadable Resiliency”, IEEE Transactions on Emerging Topics in Computing, IEEE, Vol. 6, No. 4, pp. 450 - 459, 2018. (Featured Paper)
J16 [QM’16] K. Navi, S. Khammar, S. Angizi, S. Sheikhfaal, and S. Angizi, “Excess Electron Quantum-Dot Cellular Automata Cell,” Quantum Matter, ASP, Vol. 5, no. 1, pp. 188-190, 2016.
J15 [JCS’16] F. Ahmad, G. M. Bhat, H. Khademolhosseini, S. Azimi, S. Angizi, and K. Navi, “Towards single layer quantum- dot cellular automata adders based on explicit interaction of cells”, Journal of Computational Science, Elsevier, Vol. 16, No. September 2016, pp. 8-15, 2016.
J14 [QM’16] S. Sarmadi, S. Sayedsalehi, M. Fartash, and S. Angizi, “A structured ultra-dense QCA one-bit full-adder cell”, Quantum Matter, ASP, Vol. 5, No. 1, pp. 118-123, 2016.
J13 [MICPRO’15] S. Angizi, M. H. Moaiyeri, S. Farrokhi, K. Navi, and N. Bagherzadeh, “Designing Quantum-dot Cellular Automata Counters with Energy Consumption Analysis”, Microprocessors and Microsystems, Elsevier, Vol. 39, No. 7, pp. 512-520, 2015. (Most Cited Article)
J12 [JCSC’15] S. Angizi, S. Sayedsalehi, A. Roohi, N. Bagherzadeh, and K. Navi, “Design and verification of new n-bit quantum-dot synchronous counters using majority function-based JK flip-flops”, Journal of Circuits, Systems, and Computers, World Scientific, Vol. 24, No. 10, pp. 1-17, 2015.
J11 [MEJO’15] S. Angizi, S. Sarmadi, S. Sayedsalehi, and K. Navi, “Design and evaluation of new majority gate-based RAM cell in quantum-dot cellular automata”, Microelectronics Journal, Elsevier, Vol. 46, No.1, pp. 43-51, 2015. (Most Cited Article)
J10 [MEJO’15] S. Sheikhfaal, S. Angizi, S. Sarmadi, M. H. Moaiyeri, and S. Sayedsalehi, “Designing efficient QCA logical circuits with power dissipation analysis”, Microelectronics Journal, Elsevier, Vol. 46, No. 6, pp. 462–471, 2015. (Most Cited Article)
J9 [JOLPE’15] S. Angizi, F. Danehdaran, S. Sarmadi, S. Sheikhfaal, N. Bagherzadeh, and K. Navi, “An Ultra-high Speed and Low Complexity QCA Full Adder”, Journal of Low Power Electronics, ASP, Vol. 11, No. 2, pp. 173-180, 2015.
J8 [INS’15] S. Sayedsalehi, M. Rahimi Azghadi, S. Angizi, and K. Navi, “Restoring and Non-Restoring Array Divider Designs in Quantum-dot Cellular Automata”, Information sciences, Elsevier, Vol. 311, pp. 86-101, 2015.
J7 [JHPSA’15] S. Mohammadyan, S. Angizi, and K. Navi, “New fully single layer QCA full-adder cell based on feedback model”, Int. J. of High-Performance Systems Architecture, Inderscience, Vol. 5, No. 4, pp. 202 - 208, 2015.
J6 [CTN’15] K. Navi, H. Mohammadi, and S. Angizi, “A Novel Quantum-dot Cellular Automata Reconfigurable Majority Gate with 5 and 7 Inputs Support”, Journal of Computational and Theoretical Nanoscience, ASP, Vol. 12, No. 3, pp. 399-406, 2015.
J5 [QM’15] S. Sheikhfaal, K. Navi, S. Angizi, and A. Habibizad Navin, “Designing High Speed Sequential Circuits by Quantum- Dot Cellular Automata: Memory Cell and Counter Study”, Quantum Matter, ASP, Vol. 4, No. 2, pp. 190-197, 2015.
J4 [JMEC’15] S. Sarmadi, S. Azimi, S. Sheikhfaal, S. Angizi, “Designing Counter Using Inherent Capability of Quantum-dot Cellular Automata Loops”, International Journal of Modern Education & Computer Science, Vol. 7, No. 9, pp. 22-28, 2015.
J3 [JOLPE’14] S. Angizi, E. Alkaldy, N. Bagherzadeh, and K. Navi, “Novel Robust Single Layer Wire Crossing Approach for Exclusive OR Sum of Products Logic Design with Quantum-Dot Cellular Automata”, Journal of Low Power Electronics, ASP, Vol. 10, No. 2, pp. 259-271, 2014.
J2 [CTN’14] S. Angizi, K. Navi, S. Sayedsalehi, and A. Habibizad Navin, “Efficient Quantum Dot Cellular Automata Memory Architectures Based on the New Wiring Approach”, Journal of Computational and Theoretical Nanoscience, ASP, Vol. 11, No. 11, pp. 2318-2328, 2014.
J1 [ISRN’14] A. M. Chabi, S. Sayedsalehi, S. Angizi, and K. Navi, “Efficient QCA Exclusive-or and Multiplexer Circuits Based on a Nanoelectronic-compatible Designing Approach”, International Scholarly Research Notices , Hindawi, Volume 2014, Article ID 463967, pp. 1-9, 2014.
Book Chapters
B2 S. Angizi, D. Fan, A. Marshall, and P. A. Dowben, “Nonvolatile Memory Based Architectures Using Magnetoelectric FETs,” in a Book entitled “Advances in Semiconductor Technologies: Selected Topics Beyond Conventional CMOS,” John Wiley & Sons, Inc.
B1 A. Roohi, S. Angizi, and D. Fan, “Enabling Edge Computing Using Emerging Memory Technologies: From Device to Architecture” in a Book entitled “Electronic Design for AI, IoT and Hardware Security,” Springer Nature.