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Shaahin Angizi

Assistant Professor @ NJIT


I (Shaahin Angizi) am an Assistant Professor in the Department of Electrical and Computer Engineering, New Jersey Institute of Technology (NJIT), Newark, NJ, USA, and the director of the ACAD Lab. 

I completed my doctoral studies in Electrical Engineering at the School of Electrical, Computer and Energy Engineering, Arizona State University (ASU), Tempe, AZ.

My group research interests include the cross-layer (device/circuit/architecture/algorithm/application) co-design of energy-efficient and high-performance systems with the following directions:

  • Accelerator Design for Big Data Applications: Deep Learning, Bioinformatics, Graph Processing, etc.

  • In-Memory Computing with Volatile & Non-Volatile Memories

  • Adaptive Learning for Collaborative In-Edge AI Computing IoT Systems

  • Low Power and Area-Efficient In-Sensor Computing for IoT 

  • Hardware Security Solution for Emerging Non-Volatile Memories

  • Low power VLSI circuits

Multiple Research Assistant Positions Available
I am currently looking for highly motivated and self-driven Master's & Ph.D. students for 2023!

(Click for more info)


  • [Jan 23]: Our paper “XOR-CiM: An Efficient Computing-in-SOT-MRAM Design for Binary Neural Network Acceleration” is accepted to ISQED 2023.

  • [Jan 23]: Our paper “NeSe: Near-Sensor Event-Driven Scheme for Low Power Energy Harvesting Sensors” is accepted to ISCAS 2023.

  • [Jan 23]: Our paper “Aligner-D: Leveraging in-DRAM Computing to Accelerate DNA Short Read Alignment” is accepted to IEEE JETCAS.

  • [Jan 23]: I am invited to serve as a TPC member for ISLPED 2023.

  • [Dec 22]: I am invited to serve as a TPC member for the tinyML Research Symposium 2023.

  • [Nov 22]: Our paper “P-PIM: A Parallel Processing-in-DRAM Framework Enabling RowHammer Protection” is accepted to DATE 2023.

  • [Nov 22]: Our paper “LT-PIM: An LUT-based Processing-in-DRAM Architecture with RowHammer Self-Tracking” is accepted to IEEE CAL.

  • [Oct 22]: I am invited to serve as a TPC member for DAC 2023.

  • [Oct 22]: Our paper “Ocelli: Efficient Processing-in-Pixel Array Enabling Edge Inference of Ternary Neural Networks” is accepted to Journal of Low Power Electronics and Applications.

  • [Sep 22]: Our paper “MR-PIPA: An Integrated Multi-level RRAM (HfOx) based Processing-In-Pixel Accelerator” is accepted to IEEE JXCDC.

  • [Sep 22]: NSF Grant Award received for "Collaborative Research: Integrated Sensing and Normally-off Computing for Edge Imaging Systems".

  • [Sep 22]: Our paper “semiMul: Floating-Point Free Implementations for Efficient and Accurate Neural Network Training” is accepted to ICMLA'22.

  • [Aug 22]: NSF Grant Award received for "CNS Core: Small: Toward Opportunistic, Fast, and Robust In-Cache AI Acceleration at the Edge"

  • [Aug 22]: Our paper “Energy-Efficient Recurrent Neural Network with MRAM-based Probabilistic Activation Functions” is accepted to IEEE TETC.

  • [Aug 22]: Our paper “TizBin: A Low-Power Image Sensor with Event and Object Detection Using Efficient Processing-in-Pixel Schemes” is accepted to ICCD'22.

  • [Aug 22]: Our paper “Enabling Intelligent IoTs for Histopathology Image Analysis Using Convolutional Neural Networks” is accepted to Micromachines.

  • [Aug 22]: I am invited to serve as a TPC member for ISQED 2023.

  • [July 22]: I am invited to serve as a Track Chair for VLSID 2023.

  • [July 22]: Our paper “ReD-LUT: Reconfigurable In-DRAM LUTs Enabling Massive Parallel Computation” is accepted to ICCAD'22.

  • [July 22]: Our paper “A Processing-in-Pixel Accelerator based on Multi-level HfOx ReRAM” is accepted to ESWEEK CASES'22.

  • [May 22]: Our paper “A 1.23-GHz 16-Kb Programmable and Generic Processing-in-SRAM Accelerator in 65nm” is accepted to ESSCIRC'22.

  • [May 22]: I am invited to serve as a TPC member for NOCS 2022.

  • [May 22]: Our paper “FlexiDRAM: A Flexible in-DRAM Framework to Enable Parallel General-Purpose Computation ” is accepted to ISLPED'22.

  • [May 22]: Our paper “Design and Evaluation of a Robust Power-Efficient Ternary SRAM Cell ” is accepted to MWSCAS'22.

  • [May 22]: Our paper “EaseMiss: HW/SW Co-Optimization for Efficient Large Matrix-Matrix Multiply Operations ” is accepted to DCAS'22.

  • [April 22]: I am invited to serve as a TPC member for ICCD 2022.

  • [Mar 22]: Invited to give an IEEE talk on "Towards Energy-Efficient Domain-Specific In-Sensor and In-Memory Accelerators, From Device to Algorithm".

  • [Mar 22]: I am invited to serve as a TPC member for ICCAD 2022.

  • [Mar 22]: I am invited to serve as a TPC member for ISVLSI 2022.

  • [Feb 22]: Our paper “Efficient Targeted Bit-Flip Attack Against the Local Binary Pattern Network” is accepted to HOST'22.

  • [Feb 22]: I am invited to serve as a TPC member for GLSVLSI 2022.

  • [Jan 22]: I am invited to serve as a Panelist on the Mondays in Memory (MiM) Webinar Series.

  • [Jan 22]: Our paper “SCiMA: a Generic Single-Cycle Compute-in-Memory Acceleration Scheme for Matrix Computations” is accepted to ISCAS'22.


Selected Awards and Distinctions:

2022   NSF CNS Core Grant Award

2022   NSF CCSS Grant Award

2019   Best Paper Award of 2019 ACM Great Lakes Symposium on VLSI (GLSVLSI), Washington, D.C., USA​

2018   Best Ph.D. Research Award (1st-place) of 2018 Ph.D. Forum at Design Automation Conference (DAC), San Francisco, CA, USA​

2018   Best Paper Award of 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Hong Kong, China​

2018   Featured Paper of October-December 2018 issue of IEEE Transactions on Emerging Topics in Computing​

2017   Best Paper Award of 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Bochum, Germany​

Academic Activities and Service:

Dr. Angizi has authored and co-authored more than 70 research articles in top-ranked international journals and top-tier electronic design automation conferences such as IEEE TNANO, IEEE TCAD, IEEE TC, IEEE TCASI, IEEE TETC, DAC, DATE, ICCAD, ASP-DAC, etc. He received the “Best Ph.D. research award” at the Design Automation Conference’s Ph.D. forum in 2018, two “Best Paper” awards at the IEEE Computer Society Annual Symposium on Very Large-Scale Integration (VLSI) in 2017 and 2018, and a “Best Paper” award at the ACM Great Lakes Symposium on VLSI in 2019.

He has served as a technical reviewer for over 30 international journals/conferences, such as IEEE TC, TVLSI, TCAD, TNANO, TCAS, ESL, ACM JETC, MICRO, DAC, ASP-DAC, DATE, ICCAD, ICCD, GLSVLSI, ISVLSI, etc.

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