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Shaahin Angizi

Assistant Professor @ NJIT

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I (Shaahin Angizi) am an Assistant Professor in the Department of Electrical and Computer Engineering, New Jersey Institute of Technology (NJIT), Newark, NJ, USA, and the director of the ACAD Lab. 

I completed my doctoral studies in Electrical Engineering at the School of Electrical, Computer and Energy Engineering, Arizona State University (ASU), Tempe, AZ.

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My group research interests include the cross-layer (device/circuit/architecture/algorithm/application) co-design of energy-efficient and high-performance systems with the following directions:

  • Accelerator Design for Big Data Applications: Deep Learning, Bioinformatics, Graph Processing, etc.

  • In-Memory Computing with Volatile & Non-Volatile Memories

  • Adaptive Learning for Collaborative In-Edge AI Computing IoT Systems

  • Low Power and Area-Efficient In-Sensor Computing for IoT 

  • Hardware Security Solution for Emerging Non-Volatile Memories

  • Low power VLSI circuits

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Multiple Research Assistant Positions Available
I am currently looking for highly motivated and self-driven Ph.D. students for 2024!

(Click for more info)

News:​

  • [Sep 23]: NSF Grant Award received for "CSR: Small: Cross-Layer Solutions Enabling Instant Computing for Edge Intelligence Devices". 

  • [Sep 23]: We host the 2nd Seasonal School on Intelligent Memory & Sensor at the Edge (IMS 2023) on October 10th, 2023.

  • [Aug 23]: Deniz joined ACAD Lab as a new Ph.D. student. Welcome Deniz!

  • [Aug 23]: Our paper “PiPSim: A Behavior-Level Modeling Tool for CNN Processing-in-Pixel Accelerators” is accepted to IEEE TCAD.

  • [July 23]: I am invited to give a talk at Solid-State Circuits Society (SSCS) Open Journal Webinar Series. If interested, register here.

  • [July 23]: I have been selected as an Honorary Member of the National Academy of Inventor (NAI).

  • [July 23]: I am invited to serve as a TPC member for ISQED 2024.

  • [July 23]: Our paper "Ocellus: Highly Parallel Convolution-in-Pixel Scheme Realizing Power-Delay-Efficient Edge Intelligence" has been selected as the Best Paper Candidate in ISLPED 2023.

  • [July 23]: Our paper “Design and Evaluation of a Near-Sensor Magneto-Electric FET-based Event Detector” is accepted to IEEE TED.

  • [July 23]: Our paper “PISA: A Non-Volatile Processing-In-Sensor Accelerator for Imaging Systems” is accepted to IEEE TETC.

  • [June 23]: I am invited to serve as a TPC member for ICCD 2023.

  • [June 23]: Our paper “Comparative Study of Low Bit-width DNN Accelerators: Opportunities and Challenges” is accepted to MWSCAS 2023.

  • [June 23]: Our paper “Near-Sensor Processing Accelerator for Approximate Local Binary Pattern Networks” is accepted to IEEE TETC.

  • [June 23]: ACAD Lab received the Best Paper Award in GLSVLSI 2023. Congratulations to Mehrdad and team!

  • [May 23]: Our paper “Ocellus: Highly Parallel Convolution-in-Pixel Scheme Realizing Power-Delay-Efficient Edge Intelligence” is accepted to ISLPED 2023.

  • [April 23]: Our paper "IMA-GNN: In-Memory Acceleration of Centralized and Decentralized Graph Neural Networks at the Edge" has been selected as the Best Paper Candidate in GLSVLSI 2023. Congratulations to Mehrdad!

  • [April 23]: I am invited to serve as a TPC member for ICCAD 2023.

  • [April 23]: I am invited to serve as a TPC member for NOCS 2023.

  • [Mar 23]: Two papers are accepted to GLSVLSI 2023.

  • [Mar 23]: Ranyang, Mehrdad, and Nakul presented our latest research at Computer Architecture Day at Princeton University. 

  • [Mar 23]: I am invited to serve as a TPC member for ICONS 2023.

  • [Feb 23]: I am invited to serve as a TPC member for ISVLSI 2023.

  • [Feb 23]: I am invited to serve as a TPC member for GLSVLSI 2023.

  • [Feb 23]: Our paper “AppCiP: Energy-Efficient Approximate Convolution-in-Pixel Scheme for Neural Network Acceleration” is accepted to IEEE JETCAS.

  • [Jan 23]: IEEE CAS Grant for Seasonal School on Intelligent Memory & Sensor at the Edge (IMS 2023).  

  • [Jan 23]: Our paper “XOR-CiM: An Efficient Computing-in-SOT-MRAM Design for Binary Neural Network Acceleration” is accepted to ISQED 2023.

  • [Jan 23]: Our paper “NeSe: Near-Sensor Event-Driven Scheme for Low Power Energy Harvesting Sensors” is accepted to ISCAS 2023.

  • [Jan 23]: Our paper “Aligner-D: Leveraging in-DRAM Computing to Accelerate DNA Short Read Alignment” is accepted to IEEE JETCAS.

  • [Jan 23]: I am invited to serve as a TPC member for ISLPED 2023.

                                                                                                         .

                                                                                                         .

  • [Sep 22]: NSF Grant Award received for "Collaborative Research: Integrated Sensing and Normally-off Computing for Edge Imaging Systems". 

  • [Aug 22]: NSF Grant Award received for "CNS Core: Small: Toward Opportunistic, Fast, and Robust In-Cache AI Acceleration at the Edge"

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Selected Awards and Distinctions:

2023   NSF CSR Grant Award

2023   Best Paper Award of 2023 ACM Great Lakes Symposium on VLSI (GLSVLSI), Knoxville, Tennessee, USA​

2022   NSF CNS Core Grant Award

2022   NSF CCSS Grant Award

2019   Best Paper Award of 2019 ACM Great Lakes Symposium on VLSI (GLSVLSI), Washington, D.C., USA​

2018   Best Ph.D. Research Award (1st-place) of 2018 Ph.D. Forum at Design Automation Conference (DAC), San Francisco, CA, USA​

2018   Best Paper Award of 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Hong Kong, China​

2018   Featured Paper of October-December 2018 issue of IEEE Transactions on Emerging Topics in Computing​

2017   Best Paper Award of 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Bochum, Germany​

Academic Activities and Services:

Dr. Angizi has authored and co-authored more than 100 research articles in top-ranked international journals and top-tier electronic design automation conferences such as IEEE TCAD, IEEE TC, IEEE TCASI, IEEE TETC, DAC, DATE, ICCAD, ASP-DAC, etc. He received the “Best Ph.D. research award” at the Design Automation Conference’s Ph.D. forum in 2018, two “Best Paper” awards at the IEEE Computer Society Annual Symposium on Very Large-Scale Integration (VLSI) in 2017 and 2018, and two “Best Paper” awards at the ACM Great Lakes Symposium on VLSI in 2019 and 2023. He has served as a technical reviewer for over 30 international journals/conferences, such as IEEE TC, TETC, TVLSI, TCAD, TNANO, TCAS, ESL, ACM JETC, MICRO, DAC, ASP-DAC, DATE, ICCAD, ICCD, GLSVLSI, ISVLSI, etc.

Organized Events:

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