This project can be divided into four main sub-projects:

(a) Design and evaluation of efficient QCA memory cells

In this study, we develop novel, efficient and nanotechnology-compatible QCA memory architecture for latches, flip-flops and Random Access Memory (RAM) cells as significant components of any digital system. To realize such components, we leverage QCA loop-based method, in which by circulating one bit through a four-phase closed loop, the data could be more efficiently stored.  Single-layer QCA implementation of D, T, and JK flip-flops (latches) that are highly beneficial in constructing various sequential circuits are proposed. Accordingly, highly-optimized mod-4 (2-bit), mod-8 (3-bit) and mod-16 (4-bit) synchronous counters are presented as an application based on flip-flops. In addition, new designs for QCA edge converter are proposed which are potentially applied in the proposed designs. Our works have shown significant improvements in terms latency, number of required QCA cells, area and energy consumption compared to state-of-the-art designs.

Selected Publications: [JSS'18][MICPRO'15], [MICRO'15], [JCSC'15][JCTN '14] , etc.

(b) Design and evaluation of arithmetic and logic QCA functional blocks

This study is accomplished in two distinct phases: 1- Design of QCA functional blocks, and 2- Develop of a universal interconnect methodology in order to connect functional blocks.

In the first phase, we develop primary QCA building blocks (i.e. three, five and seven-input majority gates), which can construct all Boolean expressions. Then, because of the importance of arithmetic and logic circuits as essential parts in computational and processor circuits, we develop and evaluate new implementations of QCA Adder, Subtractor, Compressor, Divider, Square root circuit and even parity generator. We use a bottom-up design approach to implement such circuits where the main design is partitioned into smaller components and each element is designed and discussed separately. In our large scale designs such as Divider and Square root, a unique pipelined structure for pumping clocks to circuits is used considering pre-defined design rules to make such circuits even more robust against unwanted noises. The proposed designs have considerable improvements in gate, cell counts, area and latency compared to counterparts.

In the second phase, a new robust single layer wire crossing method is proposed. It is well known that for a VLSI design typically interconnections among components consume the largest amount of layout area. In order for QCA to be the future substitute for CMOS (Complementary Metal-Oxide Semiconductor), the interconnection problem needs to be solved efficiently. Our new method does not involve any circuit overhead and has only one cell type and removes the need to have two cells types in the same circuit layout, an advantage that will remove a serious source of defects for the future QCA fabrication.

Selected Publications: [MICRO'15], [INS'15], [JOLPE'15], [INIS'15], etc.

(c) Analysis and design of QCA reversible architectures

Since in CMOS structure the power consumption is higher than the lower bound of heat dissipation (kTln2 joules), this technology is not suitable in implementing reversible quantum gates. Hence, in this study, we seek to propose and develop method to design QCA reversible gate to utilize in future quantum computing. In our method reversible design can be easily built upon three and five-input majority gates which are the most significant QCA components. We then propose different QCA designs which enable rich fault-tolerance features, as well as reversibility attributes sought for energy-neutral computation. All our designs are constructed based on Launder clocking scheme which provides the system with two benefits: fine-grained pipelining and high throughput.

Selected Publications: [TETC'16], [MICPRO'17] ,[CADS'15], [Optik'17]etc.

(d) Power dissipation analysis and modeling of QCA-based architectures

QCA exhibits a new paradigm at nanoscale for possible substitution of conventional CMOS technology. Most of the research works in QCA domain have completely ignored the significance of energy consumption constraint in designing circuits. The main aim of our work is to model and ultimately analyze the energy and power dissipation of QCA arithmetic/logic and memory circuits. In the first step, a comprehensive study over power and structural subjects of the previously reported majority gates (as the main component in QCA technology) is made. In the second step, we develop a QCA power model based on previous works that could efficiently estimate energy consumed by different structures dividing it into two main components (i.e., leakage and switching powers). 

Selected Publications: [JNO'18], [JOCS'16], [MICRO'15], etc.