Conference Publications

C40 [DAC21] F. Zhang, S. Angizi and D. Fan, “Max-PIM: Fast and Efficient Max/Min Searching in DRAM,” IEEE/ACM DesignAutomation Conference (DAC), San Francisco, CA, July 11-15, 2021. 

C39 [DAC21] F. Zhang, S. Angizi, N. Ahmed Fahmi, W. Zhang and D. Fan, “PIM-Quantifier: A Processing-in-Memory Platform for Genome Quantification,”IEEE/ACM Design Automation Conference (DAC), San Francisco, CA, July 11-15, 2021. 

 

C38 [SOCC’20] L. Yang, Z. He, S. Angizi and D. Fan, “Processing-In-Memory Accelerator for Dynamic Neural Network with Run-Time Tuning of Accuracy, Power and Latency,”33rd IEEE International System-on-Chip Conference (SOCC), September 8-11, 2020 (invited).

C37 [GLSVLSI’20]  S. Angizi, W. Zhang and D. Fan, “Exploring DNA Alignment-in-Memory Leveraging Emerging SOT-MRAM,”30th edition of the ACM Great Lakes Symposium on VLSI (GLSVLSI), Beijing, China, September 8-11, 2020 (Virtual).

C36 [GLSVLSI’20] D. Reis, D. Gao, S. Angizi, X. Yin, D. Fan, M. Niemier, C. Zhuo and X.S. Hu„ “Modeling and Benchmarking Computing-in-Memory for Design Space Exploration,”30th edition of the ACM Great Lakes Symposium on VLSI(GLSVLSI), Beijing, China, September 8-11, 2020 (Virtual).

 

C35 [DAC’20] S. Angizi, N. Ahmed Fahmi, W. Zhang  and D. Fan, “PIM-Assembler: A Processing-in-Memory Platform for Genome Assembly,” IEEE/ACM Design Automation Conference (DAC), San Francisco, CA, July 19-23, 2020. 

C34 [DATE’20] S. Angizi, J. Sun, W. Zhang  and D. Fan, “PIM-Aligner: A Processing-in-MRAM Platform for Biological Sequence Alignment,” Design, Automation and Test in Europe (DATE), 09-13 March 2020, ALPEXPO, Grenoble, France. 

C33 [ASPDAC’20] L. Yang, S. Angizi, and D. Fan, “A Flexible Processing-in-Memory Accelerator for Dynamic Channel-Adaptive Deep Neural Networks,” Asia and South Pacific Design Automation Conference (ASP-DAC) Jan. 13-16, 2020, Beijing, China.

C32 [ISVLSI’19] S. Angizi, Z. He, D. Reis, X. S. Hu, W. Tsai, S. J. Lin and D. Fan, “Accelerating Deep Neural Networks in Processing-in-Memory Platforms: Analog or Digital Approach?,” IEEE Computer Society Annual Symposium on VLSI (ISVLSI) , June 15-17, 2019, Las Vegas, Miami, Florida, USA.

C31 [NANOARCH’19] S. Angizi and D. Fan, “Deep Neural Network Acceleration in Non-Volatile Memory: A Digital Approach?,” IEEE/ACM International Symposium on Nanoscale Architectures, 17-19 July 2019, Qingdao, CHINA.

C30 [ICCAD’19] S. Angizi, and D. Fan, “ReDRAM: A Reconfigurable Processing-in-DRAM Platform for Accelerating Bulk Bit-Wise Operations,” IEEE/ACM International Conference on Computer Aided Design (ICCAD), 4-7 November 2019, Westminster, CO, USA.

C29 [DAC’19] S. Angizi, J. Sun, W. Zhang and D. Fan, “AlignS: A Processing-In-Memory Accelerator for DNA Short Read Alignment Leveraging SOT-MRAM,” IEEE/ACM Design Automation Conference (DAC), June 2-6, 2019, Las Vegas, NV, USA.

C28 [GLSVLSI’19] S. Angizi and D. Fan, “GraphiDe: A Graph Processing Accelerator leveraging In-DRAM-Computing,” ACM Great Lakes Symposium on VLSI (GLSVLSI) , May 9-11, 2019, Washington, D.C., USA. (Best Paper Award)

C27 [DATE’19] S. Angizi , J. Sun, W. Zhang and D. Fan, “GraphS: A Graph Processing Accelerator Leveraging SOT-MRAM,” Design, Automation and Test in Europe (DATE), March 25-29, 2019, Florence, Italy.

C26 [ASPDAC’19] S. Angizi, Z. He and D. Fan, “ParaPIM: A Parallel Processing-in-Memory Accelerator for Binary-Weight Deep Neural Networks,” Asia and South Pacific Design Automation Conference (ASP-DAC), Jan. 21-24, 2019, Tokyo, Japan.

C25 [ISQED’19] A. Roohi, S. Angizi, D. Fan and R. F. DeMara, “Processing-In-Memory Acceleration of Convolutional Neural Networks for Energy-Efficiency, and Power-Intermittency Resilience,” International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, USA, 6-7 March, 2019.

C24 [ICCD’18] A. S. Rakin, S. Angizi, Z. He and D. Fan, “PIM-TGAN: A Processing-in-Memory Accelerator for Ternary Generative Adversarial Networks,” IEEE International Conference on Computer Design (ICCD), Oct. 7-10, 2018, Orlando, FL, USA.

C23 [ICCAD’18] S. Angizi, Z. He and D. Fan, “DIMA: A Depthwise CNN In-Memory Accelerator,” IEEE/ACM International Conference on Computer Aided Design (ICCAD), Nov. 5-8, 2018, San Diego, CA, USA.

C22 [ISVLSI’18] Z. He, S. Angizi, A. S. Rakin and D. Fan, “BD-NET: A Multiplication-less DNN with Binarized Depthwise Separable Convolution,” IEEE Computer Society Annual Symposium on VLSI, July 9-11, 2018, Hong Kong, CHINA. (Best Paper Award)

C21 [ISVLSI’18] Z. He, S. Angizi and D. Fan, “Accelerating Low Bit-Width Deep Convolution Neural Network in MRAM,” IEEE Computer Society Annual Symposium on VLSI , July 9-11, 2018, Hong Kong, CHINA.

C20 [GLSVLSI’18] S. Angizi, Z. He, Y. Bai, R. F. DeMara, J. Han, M. Lin and D. Fan, “Leveraging Spintronic Devices for Efficient Approximate Logic and Stochastic Neural Network,” ACM Great Lakes Symposium on VLSI (GLSVLSI), May 23-25, 2018 Chicago, IL, USA.

C19 [DAC’18] S. Angizi , Z. He, A. S. Rakin and D. Fan, “CMP-PIM: An Energy-Efficient Comparator-based Processing-In-Memory Neural Network Accelerator,” IEEE/ACM Design Automation Conference (DAC), June 24-28, 2018, San Francisco, CA, USA.

C18 [DAC’18] S. Angizi, Z. He and D. Fan, “PIMA-Logic: A Novel Processing-in-Memory Architecture for Highly Flexible and Energy-Efficient Logic Computation,” IEEE/ACM Design Automation Conference (DAC), June 24-28, 2018, San Francisco, CA, USA.

C17 [ASPDAC’18] S. Angizi, Z. He, F. Parveen and D. Fan, “IMCE: Energy-Efficient Bit-Wise In-Memory Convolution Engine for Deep Neural Network,” Asia and South Pacific Design Automation Conference (ASP-DAC), Jan. 22-25, 2018, Jeju Island, Korea.

C16 [ASPDAC’18] F. Parveen, Z. He, S. Angizi and D. Fan, “HieIM: Highly Flexible In-Memory Computing using STT MRAM,” Asia and South Pacific Design Automation Conference (ASP-DAC), Jan. 22-25, 2018, Jeju Island, Korea.

C15 [NCAMA’17] S. Angizi and D. Fan, “IMC: Energy-Efficient In-Memory Convolver for Accelerating Binarized Deep Neural Network,” Neuromorphic Computing Symposium: Architectures, Models, and Applications, July 17-19, 2017, Knoxville, Tennessee.

C14 [ICCD’17] D. Fan and S. Angizi, “Energy Efficient In-Memory Binary Deep Neural Network Accelerator with Dual-Mode SOT-MRAM,” IEEE International Conference on Computer Design (ICCD), Nov. 5-8, 2017, Boston, MA.

C13 [ICCD’17] Z. He, S. Angizi, and D. Fan, “Exploring STT-MRAM based In-Memory Computing Paradigm with Application of Image Edge Extraction,” IEEE International Conference on Computer Design (ICCD), Nov. 5-8, 2017, Boston, MA.

C12 [ISLPED’17] F. Parveen, S. Angizi, Z. He and D. Fan, “Low Power In-Memory Computing based on Dual-Mode SOT- MRAM,” IEEE/ACM International Symposium on Low Power Electronics and Design, July 24-26, 2017, Taipei, Taiwan.

C11 [NANOARCH’17] Z. He, S. Angizi, F. Parveen and D. Fan, “High Performance and Energy-Efficient In-Memory Computing Architecture based on SOT-MRAM,” IEEE/ACM International Symposium on Nanoscale Architectures, July 25- 26, 2017, Newport, USA.

C10 [ISVLSI’17] D. Fan, S. Angizi and Z. He, “In-Memory Computing with Spintronic Devices,” IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 3-5, 2017, Bochum, Germany (invited).

C9 [ISVLSI’17] S. Angizi, Z. He, F. Parveen and D. Fan, “RIMPA: A New Reconfigurable Dual-Mode In-Memory Processing Architecture with Spin Hall Effect-Driven Domain Wall Motion Device,” IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 3-5, 2017, Bochum, Germany.

C8 [ISVLSI’17] F. Parveen, Z. He, S. Angizi and D. Fan, “Hybrid Polymorphic Logic Gate with 5-Terminal Magnetic Domain Wall Motion Device,” IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 3-5, 2017, Bochum, Germany. (Best Paper Award)

C7 [MWCAS’17] D. Fan, Z. He and S. Angizi, “Leveraging Spintronic Devices for Ultra-Low Power In-Memory Computing: Logic and Neural Network,” 60th IEEE International Midwest Symposium on Circuits and System, Aug. 6-9, 2017, Boston, MA, USA (invited)

C6 [ISCAS’17] F. Parveen, S. Angizi, Z. He and D. Fan, “Hybrid Polymorphic Logic Gate Using 6 Terminal Magnetic Domain Wall Motion Device,” IEEE International Symposium on Circuits & Systems (ISCAS), Baltimore, MD, USA, May 28-31, 2017.

C5 [GLSVLSI’17] S. Angizi, Z. He, and D. Fan, “Energy Efficient In-Memory Computing Platform Based on 4-Terminal Spin Hall Effect-Driven Domain Wall Motion Devices”, 27th GLSVLSI, Banff, Alberta, Canada, May 10-12, 2017.

C4 [GLSVLSI’17] Z. He, S. Angizi, F. Parveen, and D. Fan, “Leveraging Dual-Mode Magnetic Crossbar for Ultra-low Energy In- Memory Data Encryption”,

27th GLSVLSI, Banff, Alberta, Canada, May 10-12, 2017.

C3 [ISQED’17] S. Angizi, Z. He, R. DeMara and D. Fan, “Composite Spintronic Accuracy-Configurable Adder for Low Power Digital Signal Processing,” 18th International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, USA, 13-15 March, 2017.

C2 [CADS’15] A. M. Chabi, A. Roohi, R. F. DeMara, S. Angizi, K. Navi, and H. Khademolhosseini, "Cost-efficient QCA reversible combinational circuits based on a new reversible gate," in Computer Architecture and Digital Systems (CADS), 2015 18th IEEE CSI International Symposium on, 2015, pp. 1-6.

C1 [INIS’15] M. R. Jahangir, S. Sheikhfaal, S. Angizi, K. Navi, and F. Ahmad, Designing Nanoelectronic-compatible 8-bit Square Root Circuit by Quantum-dot Cellular Automata, In Proceeding of The IEEE International Symposium on Nanoelectronic and Information Systems, Indore, India, December 21st-23rd, 2015.